Metal oxide semiconductor (MOS) devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate an ion implanted channel region separating( the source/drain regions, and a thin gate oxide and a conductive gate formed above the channel region. A traditional approach to forming MOS devices comprises initially blanket doping the substrate with the intended channel implant before gate oxidation, forming the gate oxide and the gate, then counter-doping the source/drain regions and annealing to electrically activate the implants. However, this technique is problematic given the current demands for miniaturization and increased circuit density, which have led to a dramatic reduction in feature sizes. When feature sizes are scaled to below 1 .mu.m, the traditional approach results in devices exhibiting undesirable short-channel effects, increased junction capacitance and mobility degradation (i.e. increased resistance) in the source/drain regions due to the presence of the unneeded heavy channel implant in the source/drain regions. Furthermore, during the annealing step, transient enhanced diffusion occurs, causing accelerated diffusion of source/drain dopants into the channel and out-diffusion of channel dopants to the source/drain regions, thereby decreasing the channel doping. To compensate, a higher initial channel doping concentration is necessary. However, raising the initial channel doping level further increases junction capacitance and degrades mobility in the source/drain regions.
As a result, the traditional approach is being largely replaced with newer methodologies. In one such technique, as illustrated in FIG. 1A a thin gate oxide 20 is first formed on a substrate 10 and a conductive gate 30. typically of polysilicon, is formed over gate oxide 20. Intended source/drain regions are then masked by masks 40, and the channel region 50 is ion implanted through gate 30 with impurities 60, as shown in FIG. 1B. Thereafter, as shown in FIG. 1C, a heavy source/drain implant is performed to implant impurities 70. The implants 60, 70 are then electrically activated by heating, as by rapid thermal annealing (RTA).
Disadvantageously, bombardment of the silicon of substrate 10 with a high flux of ions during the heavy source/drain implant causes crystallographic defects 80 in silicon 10 (i.e., holes in the crystal structure). Such defects. in turn, cause unwanted diffusion of implants 60, 70, especially during the RTA process. During such diffusion, channel dopants 60 migrate under the source/drain junctions J, and defects 80 attract dopants 70 to fill holes in the silicon crystal structure, as shown in FIG. 1D. The rise in doping level under the junctions J due the diffusion undesirably increases parasitic junction capacitance, thereby degrading device performance as by decreasing circuit speed. In addition, dopant migration from the channel region creates problems in controlling the threshold voltage of the finished device thereby lowering manufacturing yield.
There exists a need for methodology enabling the manufacture of semiconductor devices with channel doping localized under the gate, thereby reducing parasitic junction capacitance, improving device performance and increasing yield.